1. Field of the Invention
The present invention relates to devices for data storage and retrieval. Particularly, this invention relates to a memory apparatus, which may be of resistive cross point memory (RXPtM) cell type (one example of which is a magnetic random access memory (MRAM)), having multiple serial data and control paths. The multiple serial data paths are merged and may exchange data as needed by the data input/output (1/0) circuits connected to a serial I/O port. A plurality of scan path registers are connected by an array of static random access memory (SRAM) memory cells to perform a parallel transfer of data from scan path registers to and from temporary registers in the SRAM memory array in order to effect data exchange between the multiple scan path registers
2. Related Technology
A scan chain is a set of registers connected in series with a facility to shift data between the registers in the series, in order to transfer data from the one end of the scan chain to the other or to perform the function of controlling the state of the registers of the scan chain, for example. An example of the use of a scan chain is to connect the I/O pads of a chip as a facility to serially transfer control data and address data applied to the input of the chip to the memory control blocks or the memory array blocks and to serially transfer output data from the memory array or control blocks to the I/O pads of the chip. One example of a serial scan chain commonly found in digital integrated circuits is a “boundary scan chain” in which the I/O for a chip or circuit block is connected to a scan chain to provide the option to extract the I/O in parallel or to extract the I/O in a serial manner by shifting the I/O to a single output port through the “boundary scan chain.”
Another form of boundary scan chain connects the parallel control and I/O functions of a system block to a small set of serial data ports. Scan chains may also be found in digital logic systems connecting all the registers of the system together as part of a scan test system. One example of a system that may contain many control and data scan chains is an MRAM memory. Such an MRAM memory would be a complete device, including system controls, with multiple local data I/O scan chains connecting together sub-blocks of the MRAM memory cell arrays, and a scan chain to connect the system I/O ports.
Prior solutions to the problem of exchanging data between plural scan chain registers have required custom designed logic circuits to perform the function of moving data from one scan chain to another. This conventional solution disadvantageously requires custom logic circuit to be designed for each application. Further, for a minimal configuration of coupling two scan chains the conventional solution may be a reasonable solution. However, for when more than two scan chains are to be coupled, then there is a need for more temporary storage as part of the scan chain data exchange circuitry. In this context, the conventional solution becomes much too complex to be practicable.
Examples of prior technology that may be relevant to the present invention are seen in U.S. Pat. No. 5,197,070, issued 23 Mar. 1993 to Hideshi Maeno; U.S. Pat. No. 5,636.228, issued 3 Jun. 1997 to Claude Moughanni, et al.; U.S. Pat. No. 5,719,504, issued 17 Feb. 1998 to Shtaka Yamada; and particularly in U.S. Pat. No. 5,953,285, issued 14 Sep. 1999 to Jonathan E. Churchill, et al. U.S. Pat. No. 5,197,070 (Maeno) is believed to use a scan path with multiple registers to affect a test function in a memory. U.S. Pat. No. 5,636,228 (Moughanni) appears to describe a tri-stateable scan register to aid in freeing up the scan chain while controlling the data output from a circuit. U.S. Pat. No. 5,719,504 (Yamada) is believed to describe a register (flip-flop) found in combinational logic that may be serially connected in a scan chain for the purpose of storing the state of the registers and allowing the contents of the registers to be shifted in and out of the circuit using a scan chain. Finally, U.S. Pat. No. 5,953,285 (Churchill) is believed to describe a control register as an interface to a memory circuit and features synchronous or asynchronous modes of operation where the register may contain a scan register.
Further, Magnetic Random Access Memory (“MRAM”) is a non-volatile memory that is being considered for long term data storage. A typical MRAM device includes an array of memory cells. Word lines extend along rows of the memory cells, and bit lines extend along columns of the memory cells. The memory cells are each located at a cross point of a word line and a bit line, and each memory cell includes two masses of magnetic material. One of the masses is magnetically fixed and the other is magnetically variable. A memory cell stores a bit of information as the orientation of relative magnetization of the fixed and variable materials. In other words, the magnetization of each memory cell at any given time assumes one of two stable orientations. These two stable orientations. referred to as “parallel” and “anti-parallel” magnetic orientation, represent logic values of ‘0’ and ‘1,’ for example. The resistance of a memory cell varies dependent upon whether it stores a “0” or a “1” value. That is, the resistance of a memory cell is a first value “R” if the orientation of the magnetization of the fixed magnetic material and of the variable magnetic material is parallel, and the resistance of the memory cell is increased to a second value R+DR if the orientation of the magnetization is anti-parallel. The orientation of the relative magnetization of a selected memory cell (and, therefore. the logic state of the memory cell) may be sensed by sensing the resistance value of the selected memory cell.
Thus, although the present invention is not so limited, an implementation of this invention may utilize MRAM memory. That is, an example of this invention may be implemented in an MRAM memory device, which memory device has control and data scan chains, as mentioned above.
Also in view of the above, it appears that there is a need for an effective and efficient solution for coupling multiple scan chains with the possibility of adding varying amounts of extra storage memory for exchanging data between the scan chains by providing a SRAM memory array at the junction of the multiple scan chains.